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PI6C20800BAEX 封裝TSSOP48 DIODES/美臺時鐘緩沖器芯片

PI6C20800BAEX 封裝TSSOP48 DIODES/美臺時鐘緩沖器芯片

PI6C20800BAEX 封裝TSSOP48 DIODES/美臺時鐘緩沖器芯片

PI6C20800BAEX 封裝TSSOP48 DIODES/美臺時鐘緩沖器芯片

PCI Express? 3.0 1:8 HCSL Clock Buffer
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通盛 產(chǎn)品介紹

Product index

PI6C20800B is a PCIe 3.0 compliant, high-speed, low-noise differential clock buffer designed to be a companion to PCI Express 3.0 clock generator for Intel server chipsets. The device distributes the differential SRC clock from PCIe clock generator to eight differential pairs of clock outputs either with or without PLL. The input SRC clock can be divided by 2 when SRC_DIV# is LOW. The clock outputs are controlled by input selection of SRC_ STOP#, PWRDWN# and SMBus, SCLK and SDA. When input of either SRC_STOP# or PWRDWN# is LOW, the output clocks are Tristated. When PWRDWN# is LOW, the SDA and SCLK inputs antimony compounds. Block Diagram

通盛 訂購信息

ordering information
器件類目 產(chǎn)品型號 封裝描述 包裝數(shù) 是否在產(chǎn) 應(yīng)用 絲印
時鐘緩沖器
PI6C20800BAEX 

TSSOP48

-

打印機和掃描儀 

PI6C20800BAEX

通盛管腳排列

Pin Configuration

resource/images/bc05c09e626d4a5b9ec0425f48393a78_44.jpg

通盛 產(chǎn)品特性

Product characteristics
3.3V Operation
PLL or Fanout operation
Power Management Control
Outputs Tristate control via SMBus
Output Enable for all outputs
Low Cycle-to-cycle jitter < 60ps
Eight Pairs of Differential Clocks
Phase jitter filter for PCIe 3.0 application

通盛 應(yīng)用范圍

Scope of application

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Tongsheng warehouse

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通盛 榮譽資質(zhì)

Honorary qualification

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